Director, Engineering

Job Details: Job Description: Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR) Intel is seeking an experienced Senior Director of Engineering to lead the Physical Design organization responsible for delivering best-in-class DDR and LPDDR Memory PHY IPs for Intel's Client, Datacenter, and Foundry/ASIC products. The successful candidate will lead a global team of more than 50 engineers across the United States, India, and Malaysia, consisting of both direct reports and matrixed resources. This leader will drive end-to-end physical implementation, execution excellence, methodology development, and technology enablement for multiple generations of high-performance memory PHY solutions spanning leading-edge process technologies including Intel 18A, Intel 14A, and future nodes. The role requires a combination of deep technical expertise in high-speed PHY design and physical implementation, strong organizational leadership, and proven experience delivering complex silicon at aggressive schedules across multiple product segments. ________________________________________ Key Responsibilities Organizational Leadership • Lead and develop a global team of 50+ Physical Design engineers located across multiple geographies. • Manage a mix of direct and matrix reporting relationships while fostering a high-performance, collaborative engineering culture. • Drive organizational growth, talent development, succession planning, and employee engagement. • Establish clear goals, execution strategies, and performance metrics aligned with business objectives. Technical Leadership • Own end-to-end Physical Design execution for DDR and LPDDR PHY IPs across multiple Intel product lines. • Drive implementation activities including: o Floorplanning o Power planning o Placement and optimization o Clock distribution o Timing closure o Signal integrity o Power integrity o Physical verification o Design signoff • Lead delivery of high-speed PHY implementations targeting industry-leading performance, power, area, and reliability metrics. • Establish and drive best-known methods (BKMs) for advanced-node implementation and signoff. Program Execution • Drive predictable execution across multiple concurrent programs supporting Client, Datacenter, and ASIC/Foundry products. • Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams. • Manage schedule, resource allocation, risk mitigation, and milestone delivery. • Ensure successful tape-in and tape-out of complex PHY IPs on aggressive product timelines. Methodology and Innovation • Champion next-generation Physical Design methodologies, automation, and AI-assisted design flows. • Drive productivity improvements through scalable automation and design reuse strategies. • Lead adoption of advanced implementation techniques required for sub-2nm technologies. • Promote technical innovation, patents, and continuous improvement initiatives. Stakeholder Engagement • Communicate effectively with senior engineering leaders, product teams, and executive management. • Drive alignment across geographically distributed organizations and external partners. • Present technical status, risks, and strategic recommendations to executive leadership. ________________________________________ Qualifications: Minimum Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline with 15+ years of industry experience; Master's or PhD preferred. • 18+ years of semiconductor design experience with significant leadership responsibility. • Proven experience leading large-scale Physical Design organizations. • Demonstrated success delivering high-speed PHY, SerDes, DDR, LPDDR, or other complex mixed-signal IPs into production. • Deep expertise in advanced node implementation including Intel 18A, Intel 14A, 2nm-class technologies, or equivalent