Senior Hardware Systems Engineer

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem.

This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.

As an Senior Hardware Systems Engineer within EverPure’s EXA Hardware Engineering organization, you will serve as a primary technical authority driving the architectural vision, end-to-end design, and system-level validation of our next-generation enterprise and cloud-scale storage platforms.

In this principal-level role, you will define the technology roadmap that bridges deep silicon/board-level hardware innovation with complex, multi-node cloud execution. You will establish design patterns, set high-speed and power/thermal benchmarks, and lead technical strategy across internal platform software teams, cross-functional executives, and global OEM/ODM/JDM partners. By defining next-generation server architectures, rack-scale power/thermal strategies, and zero-downtime resilience models, you will ensure EverPure maintains its industry-leading edge in storage performance and platform reliability.

• Architectural Leadership & Platform Strategy: Define and own the end-to-end multi-generational hardware roadmap for enterprise storage platforms. Drive architectural trade-off decisions across compute (x86/ARM), memory subsystems, DPUs, high-speed fabrics (PCIe Gen 5/6, CXL), and media technologies to maximize storage density, performance per watt, and TCO.

• JDM/ODM Governance & System Design: Lead system-level HW design reviews (schematics, layout, power tree design, thermal topology) across global OEM/ODM/JDM partners. Establish technical standards, engineering requirements documents (ERDs), and design guidelines to ensure flawless vendor execution.

• Validation Strategy & Framework Architecture: Architect overall hardware quality frameworks, comprehensive validation strategies, and advanced diagnostic models spanning parametric, functional, electrical, and full-stack software/firmware integration. Establish automated telemetry, stress-testing paradigms (e.g., FIO, SPEC, custom IO engines), and gating criteria for tier-0 production releases.

• Escalated Debug & Failure Analysis Authority: Serve as the final technical escalation point for complex, systemic hardware, signal integrity, and storage-node failures. Lead dynamic task forces across hardware, firmware, software, and silicon vendors to drive root-cause analysis (RCA) and long-term corrective action (CA) for high-impact edge cases.

• Test Automation & Tooling Infrastructure: Drive the architecture and adoption of automated test frameworks (Python/Bash) for hardware validation, L10 device-level, and L11 rack-level platform stability, continuously