Physical Design Engineer/Senior Engineer level

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation, helping create a smarter, more connected future for all. Qualcomm is seeking talented  Physical Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects spanning high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. Engineers in this role may work on different aspects of Physical Design  ASIC and SoC development, including floorplan, Clock Tree Synthesis, low power implementation, timing analysis, design methodology, automation and enabling new technology nodes. This is an excellent opportunity to join a fast-paced engineering team developing leading-edge products on advanced process technologies while collaborating with world-class design, verification, implementation, and physical design teams. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.

Overview Qualcomm Technologies' Digital ASIC team is seeking talented Physical Design Engineers to join our SoC and Core Design organization. In this role, you will be responsible for implementing complex digital designs using industry-leading methodologies and EDA tools, contributing to the delivery of high-performance and power-efficient products. You will participate in the complete physical design flow for sophisticated SoCs and IPs, including GPU, Camera, Multimedia, DDR, Modem, Audio, and other cutting-edge semiconductor solutions. This position provides the opportunity to work on advanced implementation techniques, low-power methodologies, and optimization strategies that improve performance, power efficiency, and silicon area.

Execute and drive all stages of the physical design flow from synthesized netlist to tape-out. Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs. Perform floorplanning, partitioning, power planning, and IR-drop analysis. Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios. Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations. Perform RC extraction, physical verification, and formal verification activities. Implement engineering change orders (ECOs) and support design convergence through sign-off. Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution. Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions. Develop automation and productivity tools using scripting languages and software development techniques.

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. 2+ years of industry experience or relevant academic/project experience in Physical Design.

Experience in one or more of the following areas: ASIC/SoC Physical Design implementation. Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler. Static Timing Analysis and timing closure using Synopsys PrimeTime SI. Physical verification and design sign-off methodologies. Formal verification techniques