VC Formal Staff Application Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of formal verification, and you know the difference between a proof that closes and one that explodes the state space at 2am. You understand that formal is not magic, it is a precise tool that works brilliantly when applied to the right problem with the right setup, and you have developed the instinct to know which is which. You are comfortable walking into a customer's verification environment, looking at their design blocks and assertion strategy, and quickly seeing where formal will shine and where it will struggle. Diagnosing why a formal run is slow or why convergence stalled does not frustrate you, it engages you. You think in terms of abstraction, state space, and proof complexity, and you can refactor a formal testbench so the tool can actually finish. At Synopsys, you will work directly with customers deploying VC Formal across complex SoC and IP designs, and what you recommend will directly shape how they verify their next chip.

Lead technical deployment of VC Formal at customer sites, assessing their verification environments and recommending formal methodologies that fit their design challenges Analyze customer design blocks to identify the right candidates for formal property checking, sequential equivalence, connectivity checking, and formal coverage analysis Diagnose root causes of tool performance issues and design complexity bottlenecks, then optimize formal testbench modeling to achieve proof closure Develop and deliver technical training on VC Formal features, product updates, and formal verification best practices Work with Synopsys R&D teams to communicate customer priorities and technical requirements that influence product roadmap Apply formal verification across data path logic, math function proofs, sequential equivalence checking, and formal coverage closure The Impact You Will Have Enable customers to catch critical design bugs earlier, reducing costly respins and time to tapeout Drive measurable improvements in formal tool performance and proof convergence through optimized modeling Influence the VC Formal product roadmap by translating customer pain points into actionable R&D priorities Expand formal verification adoption by demonstrating clear ROI and building internal customer champions Build reusable formal methodologies that scale across multiple customer engagements and design domains What You'll Need 4 to 8 years of hands-on experience applying formal verification in semiconductor design or verification roles Deep expertise in formal property checking, including writing assertions, constraints, and assumptions for complex digital designs Proven experience with sequential equivalence checking, formal coverage analysis, and connectivity checking methodologies Strong understanding of formal verification theory, including state space exploration, abstraction techniques, and proof convergence strategies Experience diagnosing and resolving formal tool performance issues and testbench modeling optimization Ability to assess customer verification environments and recommend tailored formal solutions Who You Are You can walk into a customer meeting, listen to their verification pain points, and sketch out a formal methodology that makes immediate sense You treat failed proofs as puzzles to solve, methodically working through abstraction and constraints until they close You can explain why an assertion is vacuous or a constraint is overconstrained