Applications Engineering, Principal Engineer
Synopsys
- Level
- Principal
- H-1B history
- 112 approvals (FY2023)
- Posted
- Aug 28, 2026
About this role
Descriptions & Requirements
Job Description and Requirements
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leadi ng silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity—p owering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the details of SoC and ASIC design, and you know the most valuable problems are solved at the intersection of customer needs, technical feasibility, and execution risk. You can walk into a room with a customer's design team, uncover the real constraints behind the ask (power, performance, area, schedule, node, packaging, ecosystem), and translate those constraints into an IP solution that will still work months later during integration and bring-up. This is a pre-sales, customer-facin g Applications Engineering (FAE) role. You will partner closely with Sales and cross-function al internal teams to drive technical discovery, solution definition, customer evaluations/PO Cs, competitive positioning, and technical closure for Interface IP opportunities across Korea. You do not just answer questions—you ask better ones. When a customer says they need a PCIe solution, you dig into their use case, process node, target data rates, channel assumptions, compliance needs, and timeline before proposing anything. You communicate with credibility: you can discuss SerDes signal integrity with a PHY engineer and then explain the business and risk tradeoffs to leadership without losing the thread. What You'll Be Doing * Own the pre-sales technical lifecycle for Interface IP opportunities across Korea: requirements discovery, solution definition, technical presentations, customer evaluation/POC planning, and technical close * Work directly with customer SoC architects and design teams to understand requirements and constraints, then recommend the right Interface IP solutions, including SerDes, PCIe, DDR, USB, MIPI, D2D, Ethernet * Lead technical evaluations and IP selection processes: define success criteria, evaluation plans, configuration recommendation s, integration approach, and risk mitigation (performance/p ower/area/sche dule) * Partner with Sales/Account teams to shape win strategies, qualify opportunities, and align on customer decision process, stakeholders, and timelines * Drive customer-facin g technical engagements such as architecture workshops, deep dives, and design reviews; coordinate follow-ups and ensure action items close on time * Support competitive situations with strong technical differentiatio n: develop positioning, handle objections, and guide customers through tradeoffs vs. alternative solutions * Drive PHY IP porting discussions and technical negotiations across process nodes and customer environments; align scope, assumptions, deliverables, and timelines with internal stakeholders * Serve as the technical bridge between customers and Synopsys R&D: translate customer issues into actionable engineering requests, drive p rioritization, and ensure timely resolution during evaluations and integration * Contribute technical inputs to proposals and commercial execution, including RFI/RFP responses, technical sections of proposals, and scope/effort inputs (as applicable) * Organize and facilitate technical forums with customers, Sales, Marketing, Program Management, and Engineering to align on strategy, resolve standoffs, and drive decisions forward * Track emerging technology trends and customer needs across AI, automotive, and data center segments; feed field insights into product roadmap and go-to-market planning The Impact You Will Have * Enable customers to de-risk SoC programs by selecting the right IP early, reducing integration issues and time-to-market delays that