Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply.

Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization Job Description The Central Engineering Group is seeking an energetic, visionary, and passionate Infrastructure AI/ ML Engineer to lead the Agentic AI Infrastructure development workflow for memory design, characterization, and yield optimization. In this role, you will collaborate with memory designers and DFT experts to build Agentic AI workflows that drive the development of state-of-the-art embedded memories optimized for PPA, DFT, and yield. Minimum Education & Experience Qualifications ● Experience: 15+ years of progressive, relevant experience in Memory design, DFT, Silicon Yield Analysis, software architecture and AI systems engineering. ● Education: Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering. Key Job Responsibilities ● Conceptualize, architect, deploy, and scale robust, distributed multi-agent AI frameworks tailored to transform intricate memory design workflows optimized for performance, power, area, and yield ● Orchestrate long-horizon, autonomous agent executions capable of managing multi-step reasoning, task decomposition, and decision-making across all phases of memory design development, silicon bring-up, and yield analysis ● Seamlessly integrate Large Language Model (LLM)-driven agent pipelines with core Electronic Design Automation (EDA) suites, custom in-house software tools, and enterprise data repositories. ● AI-Driven Debug: Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures. ● Predictive Yield Modeling: Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line. ● Partner collaboratively with Memory Design Leads, EDA Tool Specialists, and Infrastructure Engineers to distill complex, domain-specific hardware engineering methodologies into modular, goal-driven agentic workflows. ● Align AI workflow capabilities directly with organizational efficiency targets and technical milestones across the Central Engineering Group. Required Skillset & Technical Competencies ● Memory Design, Characterization and Yield Analysis: ● Experience designing and characterizing embedded memory in advanced technology process nodes ● Experience in compute-in-memory design and architecture ● AI Engineering & Multi-Agent Expertise: ● Experience architecting production-grade LLM applications: multi-agent orchestration, function-calling/tool-use, and retrieval-augmented generation (RAG). ● Experience integrating agentic systems with enterprise tools, services, and knowledge sources – including building and consuming Model Context Protocol (MCP) servers, and packaging reusable agent capabilities (e.g., Agent Skills). ● Deep experience with agent orchestration frameworks such as LangGraph. ● Semiconductor Domain Knowledge & EDA Tooling: ● Fundamental grasp of chip design methodologies, IP block development lifecycles, and verification environments. ● Hands-on familiarity with industry-standard EDA tooling and frameworks from Synopsys, Cadence, and Siemens EDA, alongside System Verilog & UVM verification environments. ● Software Engineering & Infrastructure Mastery: ● High proficiency in core programming languages and system design concepts, specifically Python and TCL. ● Expertise in microservices architecture, REST APIs, Docker, Kubernetes, Sandboxing, and config-driven workflow orchestration engine design. ● AI System Verification & Data Engineering: ● Proven experience establishing