SoC RTL Design Engineer (Up to Principal Level)

Company: Qualcomm Vietnam Company Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The SoC Design organization is seeking engineers to contribute to the integration and implementation of complex SoC and subsystem designs. This role focuses on RTL integration, design-quality assessment, synthesis, constraints, and front-end readiness for downstream implementation and verification. The successful candidate will work with IP designers, SoC architects, design verification, physical design, DFT, emulation, firmware, and methodology teams across the global engineering organization.

Integrate RTL from multiple IPs, subsystems, and reusable design components into SoC-level and subsystem-level designs. Develop and maintain top-level RTL wrappers, hierarchy, interconnect, connectivity, clock and reset structures, interrupt paths, and configuration logic. Work with standard SoC interfaces and protocols, including AXI, AHB, APB, memory, debug, interrupt, clock, reset, and power-management interfaces. Coordinate IP releases, integration dependencies, file lists, manifests, parameters, build configurations, and design collateral. Run and debug RTL compile/elaboration, lint, CDC, RDC, structural checks, formal connectivity, and synthesis flows. Prepare RTL, constraints, libraries, and configuration inputs for synthesis and downstream physical implementation. Analyze synthesis reports for timing, area, power, high-fanout, unmapped logic, inferred structures, unconnected signals, and design-rule issues. Collaborate with physical design teams to resolve critical paths, timing-convergence issues, congestion risks, and implementation constraints. Support functional equivalence, gate-level simulation, emulation, FPGA, ECO, and design-release readiness activities. Investigate failures across RTL, tools, constraints, configuration, and build environments; identify root cause and drive corrective action. Participate in design reviews, code reviews, integration reviews, methodology improvements, and technical documentation activities. Level-Specific Expectations A. Engineer: Execute defined RTL integration and synthesis tasks; resolve routine connectivity, compilation, lint, CDC, and synthesis issues with guidance; document results and escalate risks early. B. Senior Engineer: Own integration of blocks or subsystems; independently debug complex front-end issues; improve scripts and flows; coordinate effectively with partner teams. C. Staff/Senior Staff Engineer: Lead integration or synthesis activities for major subsystems or SoC components; define technical approaches; drive closure of cross-functional issues and mentor engineers. D. Principal Engineer: Provide technical leadership across programs or methodologies; influence architecture and integration strategy; drive scalable automation, quality, and synthesis convergence; mentor senior technical contributors.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 3+ years of relevant work experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or a related area. Experience with Verilog or SystemVerilog RTL development and hierarchical design integration. Experience with RTL simulation, compilation/elaboration, lint, CDC/RDC, synthesis, or equivalent front-end design flows. Knowledge of digital design fundamentals, timing concepts, clock/reset design, bus protocols, and hardware/software interfaces. Ability to analyze technical problems, communicate root cause clearly, and work effectively in a distributed, cross-functional team.

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Experience integrating complex SoCs, subsystems, infrastructure IP, NoC/interconnect, memory, debug, security, or power-management logic. Hands-on experience with synthesis, timing