RTL Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.   AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

The focus of this role is to own the top-level RTL design and integration of AMD's mixed-signal power management IP, and to drive that design through timing closure and tape-out in partnership with our physical design and verification teams.       THE PERSON:     You have a passion for digital design, mixed-signal integration, and silicon that works for the first time. You are a team player with excellent communication skills and experience collaborating with design, analog, firmware, and physical design teams. You have strong analytical and problem-solving skills, and you are ready to take ownership of hard problems.

Top-Level SOC Design   Own top-level RTL design and analog macro integration for mixed-signal power management IC   Partner with analog macro teams on block integration, including bring-up and debug of analog behavioral models in the digital simulation environment    Author micro-architecture specifications in partnership with Architecture and Firmware    Physical Design, Timing & Design Quality   Act as primary interface between RTL design and the Physical Design / timing closure team  Create and review timing constraints (SDC), including analog macro boundaries and clock-domain crossings  Drive timing closure and ECO support through tape-out; manage area, power, and floorplan tradeoffs with PD  Own RTL signoff before each release to PD: lint, CDC/RDC, synthesis QoR, and connectivity checks    Verification & Bring-Up   Partner with the verification team to define and review test plans and coverage goals  Validate analog behavioral models against analog design intent for functionality and timing, and drive discrepancies to resolution with the Analog team  Debug block- and system-level simulation failures to root cause  Support post-silicon bring-up and silicon-to-RTL correlation    Collaboration   Work across Analog, Firmware, Systems Engineering, and Architecture teams  Mentor junior engineers and lead design reviews    PREFERRED EXPERIENCE   RTL design in SystemVerilog, with ownership of blocks or subsystems through tape-out  Hands-on experience with timing constraints (SDC) development and timing closure on production silicon  Proficiency with synthesis, lint, and CDC/RDC tools and their integration into a design flow  Strong scripting skills in Python and TCL  Top-level SOC or chip-level integration ownership on a mixed-signal device  Integration and debug of analog behavioral models (Verilog-AMS, real-number/wreal modeling) in a digital simulation environment  Low-power design methodology and UPF-based power intent  Familiarity with standard control interfaces used in power management (I²C, SPI, APB, SVID/PMBus)  Post-silicon bring-up and debug experience, including silicon-to-RTL correlation    ACADEMIC CREDENTIALS:   Bachelors or master's in electrical/computer engineering     #LI-DP1 Benefits offered are described:  AMD benefits at a glance .   AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color,