Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)

Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple Design-for-Test (DFT) Engineers — ASIC Backend to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products to support advanced digital subsystem development in an aerospace environment in El Segundo or Huntington Beach, CA. Position overview The DFT team drives architecture, verification, and post-silicon validation for leading-edge ASICs. We seek engineers across experience levels (Jr → Principal) to design and validate test access mechanisms, memory BIST, scan compression, and related test infrastructure.

Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up) Integrate DFT features across the chip design flow and collaborate with cross-functional teams to ensure robust DFT integration Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable Contribute to development and deployment of DFT methodologies for next-generation products Occasional travel and after-hours meetings during critical milestones Boeing continuously shapes the future of aerospace and space systems, advancing U.S. leadership in space while amplifying human creativity and intelligence. As a Boeing engineer, you’ll join a diverse, collaborative team solving high‑impact challenges in complex semiconductor design. If you value a company that supports strong work–life balance and meaningful technical work, Boeing is the place to be. How to make your application stand out: If you are a creative, autonomous engineer passionate about advancing DFT for mission-critical ASICs, we want to hear from you. Please include a cover letter/brief summary of relevant DFT experience when submitting your application. This position is expected to be 100% onsite.  The selected candidate will be required to work onsite at one of the listed locations.

(Required Skills/Experience): This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required. Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement 2+ years of experience in Design for Testability (DFT) or equivalent (role level adjustable by experience). Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes. Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug. Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies. Excellent analytical, problem-solving, and communication skills.

(Desired Skills/Experience): Experienced, Level 3 : 5+ years of related engineering experience Lead, Level 4 : 9+ years of related engineering experience Bachelor’s Degree or Master's Degree in EE, Computer Engineering/Science, or related field Active U.S. Secret Security Clearance Requirements development and traceability experience FPGA implementation including constraints and timing closure Static timing analysis experience Understanding of timing fundamentals and CDC concepts Verification collaboration experience High-speed interfaces, processor integration, memory subsystems, or SoC