Applications Engineering, Sr. Staff Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, not just running tools but understanding why a clock tree converges or falls apart, why congestion shows up in one corner and not another, and what it actually takes to close timing at 3nm when the margin for error is measured in picoseconds. You know the difference between a flow that works on paper and one that ships silicon, and you have debugged enough failed tape-outs to spot the warning signs three weeks before they become crises. Working directly with customers energizes you. You are the engineer who can sit across from a design team struggling with a routing hotspot, pull up Fusion Compiler, and show them three ways to fix it before the meeting ends. You do not just answer questions, you ask better ones. You dig into their constraints, their schedule pressure, their process node quirks, and you help them find a path forward that actually fits their reality. You have a point of view on methodologies. You know when to push multi-scenario optimization and when to fall back to simpler techniques. At Synopsys, you will work with customers building the chips that power everything, and what you help them solve will show up in products millions of people use.

Support pre-sales and post-sales engagements with semiconductor customers, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions Debug complex physical design issues across the RTL-to-GDSII flow, working directly with customer design teams to resolve placement, routing, timing closure, and congestion challenges at advanced nodes Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure that customers can adopt in production flows Build proof-of-concept designs and benchmarks that show measurable PPA improvements using Synopsys tools compared to customer baseline flows Collaborate with product engineering teams to translate customer pain points into feature requests, tool enhancements, and methodology improvements Train customer engineers on advanced Synopsys tool capabilities, from multi-scenario optimization to noise-aware routing techniques Travel to customer sites to provide hands-on technical support during critical project phases, including tape-out preparation and bring-up The Impact You Will Have Accelerate customer adoption of Synopsys tools, directly contributing to revenue growth and competitive wins in key accounts Help customers achieve measurable improvements in PPA (power, performance, area) and reduce their time to tape-out by weeks or months through better methodologies Influence the product roadmap by surfacing real-world customer challenges that shape the next generation of Fusion Compiler and ICC2 capabilities Build long-term technical relationships with leading semiconductor companies, becoming the trusted expert they call when a design is stuck Enable customers to successfully adopt advanced node technologies (5nm, 3nm, and beyond) where traditional methodologies break down Expand Synopsys footprint within accounts by demonstrating value across multiple design teams and product lines Contribute to the technical reputation of Synopsys in the industry through customer success stories, white papers, and conference presentations What You'll Need Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience,