Physical design Staff Application engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, working on chips that actually tape out and ship in products people use. The difference between a design that closes timing and one that burns three months of schedule is something you can see coming in the floorplan stage, and you are the kind of engineer who speaks up before it becomes a crisis. You know Fusion Compiler or ICC2 well enough that you can debug a routing congestion issue at 9pm on a customer call and walk out with a plan that actually works. Scripting is not a side skill for you, it is how you think. You build flows in TCL and Python that do not just automate tasks but make design decisions smarter and more predictable. When someone says "the tool is doing something weird," you are the one who digs into the log files, finds the root cause, and writes the fix that prevents it from happening again. You are comfortable working directly with customers, not just handing off a deck but sitting in the room, understanding their constraints, and building solutions that fit their reality. At Synopsys, you will work on the hardest physical design problems in the industry, on the most advanced nodes, with customers who are building the chips that power everything.

Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraints Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not generic best practices but solutions that fit their specific context Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve implementation challenges that traditional methods struggle with Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature enhancements that make it into the next release Travel to customer sites as needed to provide onsite support, training, and design reviews, often under tight deadlines and high-stakes tape-out pressure The Impact You Will Have Enable customers to achieve timing closure and tape-out success on advanced-node designs that define next-generation AI, mobile, and datacenter products Build automation and methodology improvements that get reused across multiple customer engagements, multiplying your impact across dozens of designs Shape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&D, influencing features that thousands of engineers will use Reduce design cycle time and improve PPA outcomes for customers working at the cutting