Physical Implementation, Staff Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years turning gate-level netlists into actual silicon that works, and you know that the difference between a block that tapes out clean and one that comes back with a respin is usually a floor plan decision made in week two. You think in terms of power domains, clock trees, and routing congestion before anyone asks you to, because you have debugged enough DRC violations at 2 a.m. to know what breaks and why. You are the engineer who can look at a block, see the macro placement problem before it becomes a timing problem, and fix it without waiting for someone to tell you it is broken. You have owned gate-to-GDSII flows end to end, not just run scripts but actually understood what each step does and why it matters for signoff. You do not need hand-holding on MCMM setup or UPF constraints. You write them, you own them, and you know when they are wrong because the results tell you. When STA comes back with a violation or layout flags an antenna issue, you are the one who digs in, finds the root cause, and closes it. At Synopsys, you will work on real ASIC blocks that ship in products, with access to the toolset that defines the industry and a team that expects you to know your craft.

Implement digital blocks from gate-level netlist through GDSII using full ASIC physical design flow including design initialization, power planning, floor planning, macro placement, scan-chain reordering, clock tree synthesis, routing, and chip finishing Perform signoff verifications including DRC, LVS, and antenna checks for layout, and EMIR and ESD analysis for reliability on implemented blocks Write and own MCMM (multi-corner multi-mode) and UPF (Unified Power Format) constraint files for block-level designs Provide clean handoff data to STA, Formality, and layout and reliability verification teams to enable signoff closure Debug and resolve physical design issues related to timing, power, signal integrity, and manufacturability across advanced FinFET process nodes Collaborate with front-end design, verification, and signoff teams to ensure block-level implementation meets performance, power, and area targets Drive design closure on complex blocks, balancing trade-offs between timing, congestion, power, and physical constraints The Impact You Will Have Enable successful tape-outs of ASIC blocks that power Synopsys IP and EDA products used across the semiconductor industry Reduce design iteration cycles by delivering clean physical implementations that pass signoff verifications on the first pass Improve design quality and robustness by catching and resolving floor plan, power, and routing issues early in the implementation flow Accelerate time-to-market for Synopsys products by providing reliable handoff data that enables faster STA and verification closure Contribute to the development and refinement of ASIC design methodologies and flows used across multiple product teams Mentor and guide junior engineers on physical design best practices, signoff requirements, and debugging techniques Help shape the technical direction of ASIC implementation strategies for next-generation FinFET and advanced node designs What You'll Need Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or equivalent field 5+ years of hands-on experience in ASIC physical design, specifically gate-to-GDSII implementation flows Deep understanding of physical design stages including floor planning, power planning,