Staff Analog Design Engineer, TX/RX Datapath

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together , we can help shape the endless possibilities of AI.

Overview You will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet — the interconnect that lets our inference accelerators scale beyond a single package. This is a hands-on, transistor-level design role on a small team, where you will personally carry blocks from specification through silicon characterization rather than handing specs off to someone else. The work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon.

Own transistor-level design of the SerDes transmit path: output drivers (SST and/or CML), pre-driver and serializer stages, and transmit-side FFE. Own transistor-level design of the receive front-end: termination and ESD-aware input network, CTLE, VGA, samplers, and where applicable ADC-based front-ends. Design and verify the equalization path — DFE and FFE architecture, tap resolution, and adaptation behavior — and own the trade study behind the architecture you choose. Derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets, and defend those specifications in design review. Build the verification environment for your blocks — testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification, supporting backend engineers through integration. Perform link and channel modeling in MATLAB, Python, or equivalent — S-parameter channel and package models, statistical eye and BER analysis, and equalization trade studies. Drive layout of your blocks in deep sub-micron nodes, working with layout engineers on floorplan, matching, shielding, current density, and parasitic control, and co-designing with package/signal-integrity engineers on bump maps, escape routing, and channel budgets. Contribute to testboard design, then take your blocks through silicon bring-up and bench characterization, correlating measured performance against simulation.

BS/MS/PhD in Electrical Engineering, with 8+ years of hands-on analog and mixed-signal circuit design experience. Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link. Deep knowledge of high-speed driver design, receive front-end design, and equalization, with practical familiarity with the adjacent clocking and CDR blocks your datapath interfaces with. Practical command of jitter and noise analysis — decomposition, budgeting, and the simulation methodology to quantify each contributor. Circuit design experience in advanced FinFET or GAA process nodes, with hands-on use of industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation) and link/channel modeling (e.g., MATLAB, Python, S-parameter models). Silicon bring-up and bench debug experience with high-speed lab equipment such as scopes and BERTs, with the judgment to distinguish a design problem from a measurement problem. Preferred Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D