Principal Engineer, Inference Memory and Storage Systems

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We are looking for a Principal Engineer to own the technical vision and roadmap for the memory and storage layer underneath DigitalOcean's inference platform.

DigitalOcean is the Inference Cloud. The Inference Platform team builds the serving stack that runs frontier open models on our GPU fleet at production scale—model orchestration, disaggregated prefill and decode, request routing, and the engine integrations (vLLM, SGLang, TensorRT-LLM) that make it all go. As context lengths grow and agentic traffic patterns become the norm, the single biggest lever on cost, TTFT, and throughput is where the KV cache lives and how efficiently we can move it.

That layer is currently a collection of good decisions made independently. This role exists to make it one system: a unified, multi-tier memory and storage substrate spanning GPU HBM, host DRAM, local NVMe, and remote object storage, exposed through a coherent interface to every serving engine and router we run. The selected candidate will set direction across teams, contribute meaningfully to the open source projects we depend on, and translate hard systems work into unit economics our customers feel.

• Defining and evolving a unified memory layer spanning GPU memory, pinned host memory, RDMA-accessible memory, local NVMe tiers, and remote object storage for large-scale LLM inference

• Architecting deep integrations with the serving engines we run in production (vLLM, SGLang, TensorRT-LLM), focused on KV cache offload, reuse, eviction policy, and cross-node sharing

• Designing the interfaces and protocols behind disaggregated prefill/decode, peer-to-peer KV cache transfer, and cache-aware routing—including how the router, the engine, and the cache tier agree on what is resident and where

• Owning the eviction and admission story across tiers (LRU and its successors, cost-aware policies, pluggable backends) and the metrics that prove those policies work under real traffic

• Partnering with our GPU infrastructure, networking, and platform teams to exploit GPUDirect, RDMA, NVMe-oF, and NVLink for low-latency cache access across heterogeneous accelerator pools

• Driving the unit economics: modeling and validating the effect of cache hit ratio, prefix caching, and tiering on $/token and $/GPU-hr, and making the tradeoffs legible to product and pricing partners

• Setting technical direction and raising the bar through design review, mentorship of senior and staff engineers, and sponsorship of the initiatives that follow from this roadmap

• Representing DigitalOcean externally—upstream contributions, conference talks, and customer-facing technical deep dives

• 15+ years building large-scale distributed systems, high-performance storage, or ML systems infrastructure, with a track record of delivering and operating production services

• Deep fluency in memory hierarchies (GPU HBM, host DRAM, NVMe, remote/object storage) and experience designing systems that span tiers for both performance and cost

• Experience with distributed caching or key-value systems, particularly designs optimized for low latency under high concurrency

• Hands-on work with networked I/O and RDMA / NVMe-oF / NVLink-class technologies, and