Senior RTL Design Engineer

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science

• 5+ years of experience in ASIC RTL design

• Solid foundation in computer architecture and digital logic design

• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs

• Experience making design decisions that trade off power, performance, and area

• Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR

• Experience with digital logic synthesis tools and static timing analysis

• Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking

• Experience implementing SystemVerilog Assertions to check design intent

• Familiarity with tools and simulators for hardware performance analysis and tuning

• Familiarity with Git for managing release cycles

• Scripting skills in Python and Linux shell

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science

• Exposure to a full ASIC development cycle through tape-out and production silicon

• Interest in or knowledge of AI workload acceleration techniques

• Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes

• Exposure to emulation or FPGA prototyping platforms for pre-silicon validation

Base Pay Range

$120,000—$200,000 USD

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