Staff Analog Design Engineer, SerDes Clocking

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together , we can help shape the endless possibilities of AI.

Overview This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization. The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and firmware teams to close timing, jitter budgets, and calibration across the full SerDes macro.

Own transistor-level design of low-jitter frequency synthesis — LC and/or ring PLL, including loop filter, charge pump or digital loop, VCO, and divider chain. Own the phase interpolator and phase rotation scheme, including INL/DNL, glitch behavior, and interpolation resolution against the CDR's needs. Design high-frequency clock distribution across the SerDes macro: buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation. Define and verify CDR architecture and loop dynamics — bandwidth, jitter tolerance, jitter transfer, lock acquisition, and frequency offset tracking — modeling loop behavior in MATLAB, Python, or equivalent, and correlating against transistor-level and silicon results, in coordination with datapath and DSP owners. Build phase-noise and jitter budgets for the link and own the analysis showing where jitter originates. Build the verification environment for your blocks — PSS/HB and transient noise analysis, PVT corner coverage, Monte Carlo, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification. Drive layout of your blocks in deep sub-micron nodes, with particular attention to inductor and VCO layout, shielding, symmetry, and supply/substrate isolation. Take your blocks through silicon bring-up and bench characterization — phase noise, jitter tolerance, lock range — and correlate measured results against simulation.

BS/MS/PhD in Electrical Engineering, with 5+ years of hands-on analog and mixed-signal circuit design experience. Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link. Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory, along with working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer. Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation. Circuit design experience in advanced FinFET or GAA process nodes, using industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation). Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs. Preferred Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including clocking architecture choices specific to short-reach, low-energy-per-bit links. Forwarded-clock and matched-source-synchronous architectures alongside